Data buses are used for digital communication between two or more electronic devices. A device connected to a bus is often referred to as bus node. In general, the expression “bus” usually denotes a communication system comprising both the specification of the bus hardware and a communication protocol according to which the bus nodes communicate. Many data buses are standardized, with different bus standards prevailing in different areas of industry. By way of example, CAN (Controller Area Network), LIN (Local Interchange Network) and FlexRay are often used in the automotive industry. USB (Universal Serial Bus) is widely used in the field of consumer electronics.
A bus node (i.e. an electronic device connected to the bus) usually comprises a bus interface (e.g. an electronic circuit) that realizes the actual transmission of data to the bus and the reception of data from the bus according to the respective bus standard. A bus interface can comprise a bus driver circuit used for implementing the data transmission at the physical level (e.g. layer 1 of the known OSI model). In this case, the bus driver has to provide defined states at the physical connections to the bus line (or the bus lines). By way of example, the bus driver generates a defined first voltage level (e.g. 0 volts) in order to transmit a binary “0” via the bus, and a defined second voltage level (e.g. 12 volts) in order to transmit a binary “1” via the bus.
In many standardized buses, the bus driver can assume at least one “high-impedance” state in order to avoid problems if different bus nodes generate contradictory voltage levels on the bus lines. Tri-state bus drivers are sometimes used. However, many standardized buses use only two states (in order to represent a binary “0” and a “1”), wherein in one state (e.g. the binary “1”) the voltage level (e.g. 12 volts) is applied to the bus line (or the bus lines) via a resistor. This state is referred to as “recessive” or “idle”. A second state (e.g. the binary “0”) is called “dominant” or “active” because in this state the voltage level (e.g. 0 volts) is applied to the bus line via a low-impedance current path, for example by means of a closed semiconductor switch. In a case in which a bus node generates a “dominant” (“active”) state by a voltage level of 0 volts being constrained on the bus line, all other bus nodes which simultaneously generate a “recessive” (“idle”) state are overridden. Their output is protected by the resistor mentioned. Only the terms “recessive” and “dominant” will now be used hereinafter to describe the states at the output of a bus driver.
In all bus systems, the bus nodes (i.e. the bus driver circuits thereof) have to be able to generate a recessive state and a dominant state in order to enable collision-free communication. By way of example, in LIN or CAN systems, the recessive state represents a binary “1”, wherein the dominant state represents a binary “0”. In FlexRay or USB systems, the recessive state is usually referred to as “idle” and represents a period without communication. Although this recessive idle state is not assigned to a data bit (in FlexRay and USB systems, both “1” and “0” are dominant states), the transitions from a dominant to the recessive state are specified in the respective bus standard. For example, the transitions have to meet the timing requirements specified in the standard.
Bus driver circuits usually comprise one or more semiconductor switches configured to connect and disconnect the bus line (or bus lines) to and from a supply potential or ground potential (either via a resistor or with low impedance). However, the bus line (bus lines) can also have a significant resistance and, in particular, a capacitance, which has an influence on the switching time between a dominant and a recessive state. Consequently, the switching time is dependent not only on the characteristics of the driver circuit, but also on the properties of the connected bus line. Slow transitions to a recessive state can be problematic if high data rates are desired. Furthermore, reflections can occur at the individual bus nodes, said reflections interfering with the output signal at another bus node. Undesired oscillations can also occur during a transition from a dominant to a recessive state.